33 lines
572 B
Systemverilog
33 lines
572 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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extern program ex_pgm;
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extern interface ex_ifc;
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extern module ex_mod;
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module t;
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ex_pgm u_pgm();
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ex_ifc u_ifc();
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ex_mod u_mod();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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// Could be in another compile run, but we don't support that
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program ex_pgm;
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endprogram
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interface ex_ifc;
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endinterface
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module ex_mod;
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endmodule
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