23 lines
471 B
Systemverilog
23 lines
471 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Ryszard Rozak
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// SPDX-License-Identifier: CC0-1.0
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module dut
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#(parameter int P [5])
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(output int x);
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assign x = P[2];
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endmodule
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module t();
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int o;
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dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o));
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initial begin
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if (o !== 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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