24 lines
585 B
Systemverilog
24 lines
585 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// IEEE parameter_port_declaration has data_type but not data_type_or_implicit
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module sub1 #([7:0] PAR1 = 1); // <--- Error: requires 'parameter'
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endmodule
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module sub2 #(parameter real PAR1 = 1.0, signed PAR2 = 2);
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endmodule
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module sub3 #(localparam real PAR1 = 1.0, signed PAR2 = 2);
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endmodule
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module t;
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sub1 sub1();
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sub2 sub2();
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sub3 sub3();
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initial $stop;
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endmodule
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