27 lines
592 B
Systemverilog
27 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module sub
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#(
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parameter int unsigned VAL[2] = '{1, 2}
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)
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();
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endmodule
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module t;
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sub sub12 ();
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sub #(.VAL ( '{3, 4} )) sub34 ();
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initial begin
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if (sub12.VAL[0] != 1) $stop;
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if (sub12.VAL[1] != 2) $stop;
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if (sub34.VAL[0] != 3) $stop;
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if (sub34.VAL[1] != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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