28 lines
496 B
Systemverilog
28 lines
496 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface QBus(input logic k);
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logic data;
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endinterface
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class cls;
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virtual QBus vif1;
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function void foo(virtual QBus vif2);
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vif2.data = 1;
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endfunction
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endclass
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module t;
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cls bar;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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