31 lines
621 B
Systemverilog
31 lines
621 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface mem_if #(
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int unsigned ADDR_SIZE = 16
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);
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endinterface
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module t;
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class Cls #(
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type T = int
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);
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endclass
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// Note the referred-to virtual class is only used here, not instantiated
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typedef Cls#(virtual mem_if #(8)) cls_mem_if_t;
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typedef Cls#(virtual mem_if #()) cls_def_if_t;
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initial begin
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cls_mem_if_t c;
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cls_def_if_t d;
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c = new;
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d = new;
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$finish;
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end
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endmodule
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