34 lines
588 B
Systemverilog
34 lines
588 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface inf;
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int v;
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task setup();
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v = 3;
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endtask
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endinterface
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interface inf2;
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int k;
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endinterface
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module GenericModule (interface a);
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initial begin
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#1;
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if (a.v != 3) $stop;
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end
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endmodule
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module t;
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inf inf_inst();
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GenericModule genericModule (inf_inst);
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initial begin
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inf_inst.setup();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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