verilator/test_regress/t/t_inst_missing_dot_bad.v

13 lines
334 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
$display("a=", missing.a);
end
missing missing(); // Intentionally missing
endmodule