27 lines
769 B
Systemverilog
27 lines
769 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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localparam int unsigned LARGE_ARRAY[5] = '{1, 2, 3, 4, 5};
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localparam int unsigned SMALL_ARRAY[2] = LARGE_ARRAY[1+:2];
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sub #(.VAL(SMALL_ARRAY)) u_sub ();
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endmodule
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module sub #(
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parameter int unsigned VAL[2] = '{1, 2}
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) ();
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initial begin
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`checkd(VAL[0], 2);
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`checkd(VAL[1], 3);
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$finish;
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end
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endmodule
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