11 lines
277 B
Systemverilog
11 lines
277 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5};
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initial $finish;
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endmodule
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