12 lines
434 B
Systemverilog
12 lines
434 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (input logic[31:0] in, output logic[31:0] out);
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assign out = in;
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endmodule
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