35 lines
609 B
Systemverilog
35 lines
609 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Iru Cai
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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int ctr;
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task run();
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$display("%d", ctr);
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ctr = ctr + 1;
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endtask: run
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endclass;
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class Cls2 extends Cls1;
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task runtask();
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run();
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run();
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run();
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run();
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run();
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run();
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endtask: runtask
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endclass
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module top;
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Cls2 o;
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initial begin
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o = new;
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o.runtask();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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