32 lines
634 B
Systemverilog
32 lines
634 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class uvm_sequence_library #(
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type REQ = int,
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RSP = int
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);
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int sequences[$];
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endclass
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class Cls extends uvm_sequence_library;
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static int m_typewide_sequences[$];
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function void init_sequence_library();
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foreach (m_typewide_sequences[i]) sequences.push_back(m_typewide_sequences[i]);
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endfunction
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endclass
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initial begin
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Cls c;
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c = new;
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$finish;
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end
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endmodule
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