16 lines
324 B
Systemverilog
16 lines
324 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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endclass
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class Bar #(type BASE=Foo) extends BASE;
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task body();
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int v = 0;
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v = 1;
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endtask
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endclass
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