26 lines
594 B
Systemverilog
26 lines
594 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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typedef enum bit {A = 0, B = 1} enum_t;
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class Converter #(type T);
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function int toInt(T t);
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return int'(t);
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endfunction
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endclass
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module t;
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initial begin
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Converter#(enum_t) conv1 = new;
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Converter#(bit) conv2 = new;
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if (conv1.toInt(A) != 0) $stop;
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if (conv2.toInt(1) != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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