26 lines
490 B
Systemverilog
26 lines
490 B
Systemverilog
// DESCRIPTION: Verilator: SystemVerilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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enum logic [2:0] {S0, S1, S2} state;
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int v = 0;
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initial begin
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state = S1;
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unique case (state)
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S0, S2: $stop;
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S1: v++;
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endcase
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unique case (state)
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S2: $stop;
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default: v++;
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endcase
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end
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endmodule
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