verilator/test_regress/t/t_assert_synth_parallel.vlt

10 lines
279 B
Plaintext

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0
`verilator_config
parallel_case -file "t/t_assert_synth.v" -lines 55