33 lines
780 B
Systemverilog
33 lines
780 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input a,
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input clk
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);
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global clocking @(posedge clk);
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endclocking
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assert property (@(posedge clk) 1 == 1)
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else $display("Future=%0d", $future_gclk(a));
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assert property (@(posedge clk) 1 == 1)
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else $display("Future=%0d", $rising_gclk(a));
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assert property (@(posedge clk) 1 == 1)
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else $display("Future=%0d", $falling_gclk(a));
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assert property (@(posedge clk) 1 == 1)
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else $display("Future=%0d", $steady_gclk(a));
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assert property (@(posedge clk) 1 == 1)
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else $display("Future=%0d", $changing_gclk(a));
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initial $stop;
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endmodule
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