56 lines
1.3 KiB
Systemverilog
56 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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bit [3:0] val = 0;
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event e1;
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event e2;
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integer cyc = 1;
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always @(negedge clk) begin
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val <= 4'(cyc % 4);
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if (cyc >= 0 && cyc <= 4) begin
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->e1;
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`ifdef TEST_VERBOSE
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$display("[%0t] triggered e1", $time);
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`endif
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end
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if (cyc >= 5 && cyc <= 10) begin
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->e2;
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`ifdef TEST_VERBOSE
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$display("[%0t] triggered e2", $time);
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`endif
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end
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`ifdef TEST_VERBOSE
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$display("cyc=%0d val=%0d", cyc, val);
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`endif
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cyc <= cyc + 1;
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if (cyc == 100) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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cover property (@(e1) ##1 val[0])
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$display("[%0t] cover property, fileline:%0d", $time, `__LINE__);
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cover property (@(e1) ##1 val[0])
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$display("[%0t] cover property, fileline:%0d", $time, `__LINE__);
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cover property (@(e2) not ##1 val[1])
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$display("[%0t] not cover property, fileline:%0d", $time, `__LINE__);
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cover property (@(posedge clk) ##3 val[0] && val[1])
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$display("[%0t] concurrent cover, fileline:%0d", $time, `__LINE__);
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endmodule
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