16 lines
318 B
Systemverilog
16 lines
318 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int x1;
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initial begin
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t1(x1);
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$finish;
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end
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task t1(ref int x);
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x = #1 1;
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endtask
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endmodule
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