verilator/test_regress/t/t_variable_order_mtask.py

56 lines
2.0 KiB
Python
Executable File

#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2026 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = test.obj_dir + "/t_variable_order_mtask.v"
def gen(filename, nregs):
with open(filename, 'w', encoding="utf8") as fh:
fh.write("// Generated by t_variable_order_mtask.py\n")
fh.write("module t(input logic clk, input logic [7:0] i, output logic [31:0] o);\n")
for i in range(nregs):
fh.write(f" logic [31:0] r{i};\n")
for i in range(nregs):
fh.write(" always_ff @(posedge clk) begin\n")
fh.write(f" r{i} <= (r{i} + {{24'd0, i}}) ^ 32'h{i + 1:08x};\n")
fh.write(" end\n")
fh.write(" always_comb begin\n")
fh.write(" o = 32'h0")
for i in range(nregs):
fh.write(f" ^ r{i}")
fh.write(";\n")
fh.write(" end\n")
fh.write("endmodule\n")
gen(test.top_filename, 24)
flags = ["--cc", "--stats", "-Wno-UNOPTTHREADS"]
if test.vltmt:
flags += ["--threads-max-mtasks 8"]
test.compile(verilator_flags2=flags, threads=(2 if test.vltmt else 1))
root_h = test.obj_dir + "/" + test.vm_prefix + "___024root.h"
aligned_var_re = r'alignas\(VL_CACHE_LINE_BYTES\) (?:CData|SData|IData|QData|VlWide|VL_)'
if test.vltmt:
test.file_grep(root_h, aligned_var_re)
test.file_grep(test.stats, r'VariableOrder, MTask affinity groups\s+([1-9]\d*)')
test.file_grep(test.stats, r'VariableOrder, MTask aligned group starts\s+([1-9]\d*)')
else:
test.file_grep_not(root_h, aligned_var_re)
test.file_grep_not(test.stats, r'VariableOrder, MTask affinity groups')
test.file_grep_not(test.stats, r'VariableOrder, MTask aligned group starts')
test.passes()