705 lines
23 KiB
Systemverilog
705 lines
23 KiB
Systemverilog
// ======================================================================
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// ======================================================================
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`define STRINGIFY(x) `"x`"
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`ifdef VERILATOR_COMMENTS
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`define PUBLIC_FORCEABLE /*verilator public_flat_rw*/ /*verilator forceable*/
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`else
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`define PUBLIC_FORCEABLE
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`endif
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module t;
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reg clk;
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initial begin
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clk = 0;
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forever #1 clk = ~clk;
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end
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Test test (.clk(clk));
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endmodule
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module Test (
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input clk
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);
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`ifdef IVERILOG
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`elsif USE_VPI_NOT_DPI
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`ifdef VERILATOR
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`systemc_header
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extern "C" int putString();
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extern "C" int tryInvalidPutOperations();
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extern "C" int putInertialDelay();
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extern "C" int forceValues();
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extern "C" int releaseValues();
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extern "C" int releasePartiallyForcedValues();
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extern "C" int checkValuesForced();
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extern "C" int checkValuesPartiallyForced();
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extern "C" int checkValuesReleased();
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`verilog
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`endif
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`else
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`ifdef VERILATOR
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import "DPI-C" context function int putString();
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import "DPI-C" context function int tryInvalidPutOperations();
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import "DPI-C" context function int putInertialDelay();
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`endif
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import "DPI-C" context function int forceValues();
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import "DPI-C" context function int releaseValues();
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import "DPI-C" context function int releasePartiallyForcedValues();
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import "DPI-C" context function int checkValuesPartiallyForced();
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import "DPI-C" context function int checkValuesForced();
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import "DPI-C" context function int checkValuesReleased();
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`endif
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// Verify that vpi_put_value still works for strings
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string str1 /*verilator public_flat_rw*/; // std::string
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// Verify that vpi_put_value still works with vpiInertialDelay
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logic [ 31:0] delayed `PUBLIC_FORCEABLE; // IData
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// Clocked signals
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// Force with vpiIntVal
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logic onebit `PUBLIC_FORCEABLE; // CData
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logic [ 31:0] intval `PUBLIC_FORCEABLE; // IData
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// Force with vpiVectorVal
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logic [ 7:0] vectorC `PUBLIC_FORCEABLE; // CData
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logic [ 61:0] vectorQ `PUBLIC_FORCEABLE; // QData
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logic [127:0] vectorW `PUBLIC_FORCEABLE; // VlWide
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// Force with vpiRealVal
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real real1 `PUBLIC_FORCEABLE; // double
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// Force with vpiStringVal
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logic [ 15:0] textHalf `PUBLIC_FORCEABLE; // SData
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logic [ 63:0] textLong `PUBLIC_FORCEABLE; // QData
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logic [511:0] text `PUBLIC_FORCEABLE; // VlWide
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// Force with vpiBinStrVal, vpiOctStrVal, vpiHexStrVal
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logic [ 7:0] binString `PUBLIC_FORCEABLE; // CData
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logic [ 14:0] octString `PUBLIC_FORCEABLE; // SData
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logic [ 63:0] hexString `PUBLIC_FORCEABLE; // QData
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// Force with vpiDecStrVal
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logic [ 7:0] decStringC `PUBLIC_FORCEABLE; // CData
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logic [ 15:0] decStringS `PUBLIC_FORCEABLE; // SData
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logic [ 31:0] decStringI `PUBLIC_FORCEABLE; // IData
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logic [ 63:0] decStringQ `PUBLIC_FORCEABLE; // QData
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// Continuously assigned signals:
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// Force with vpiIntVal
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wire onebitContinuously `PUBLIC_FORCEABLE; // CData
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wire [ 31:0] intvalContinuously `PUBLIC_FORCEABLE; // IData
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// Force with vpiVectorVal
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wire [ 7:0] vectorCContinuously `PUBLIC_FORCEABLE; // CData
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wire [ 61:0] vectorQContinuously `PUBLIC_FORCEABLE; // QData
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wire [127:0] vectorWContinuously `PUBLIC_FORCEABLE; // VlWide
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// Force with vpiRealVal
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`ifdef IVERILOG
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// Need wreal with Icarus for forcing continuously assigned real
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wreal real1Continuously `PUBLIC_FORCEABLE; // double
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`else
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real real1Continuously `PUBLIC_FORCEABLE; // double
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`endif
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// Force with vpiStringVal
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wire [ 15:0] textHalfContinuously `PUBLIC_FORCEABLE; // SData
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wire [ 63:0] textLongContinuously `PUBLIC_FORCEABLE; // QData
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wire [511:0] textContinuously `PUBLIC_FORCEABLE; // VlWide
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// Force with vpiBinStrVal, vpiOctStrVal, vpiHexStrVal
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wire [ 7:0] binStringContinuously `PUBLIC_FORCEABLE; // CData
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wire [ 14:0] octStringContinuously `PUBLIC_FORCEABLE; // SData
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wire [ 63:0] hexStringContinuously `PUBLIC_FORCEABLE; // QData
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// Force with vpiDecStrVal
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wire [ 7:0] decStringCContinuously `PUBLIC_FORCEABLE; // CData
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wire [ 15:0] decStringSContinuously `PUBLIC_FORCEABLE; // SData
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wire [ 31:0] decStringIContinuously `PUBLIC_FORCEABLE; // IData
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wire [ 63:0] decStringQContinuously `PUBLIC_FORCEABLE; // QData
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always @(posedge clk) begin
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onebit <= 1;
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intval <= 32'hAAAAAAAA;
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vectorC <= 8'hAA;
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vectorQ <= 62'h2AAAAAAA_AAAAAAAA;
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vectorW <= 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA;
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real1 <= 1.0;
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textHalf <= "Hf";
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textLong <= "Long64b";
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text <= "Verilog Test module";
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binString <= 8'b10101010;
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octString <= 15'o25252; // 0b1010...
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hexString <= 64'hAAAAAAAAAAAAAAAA; // 0b1010...
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decStringC <= 8'hAA;
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decStringS <= 16'hAAAA;
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decStringI <= 32'hAAAAAAAA;
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decStringQ <= 64'd12297829382473034410; // 0b1010...
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end
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assign onebitContinuously = 1;
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assign intvalContinuously = 32'hAAAAAAAA;
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assign vectorCContinuously = 8'hAA;
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assign vectorQContinuously = 62'h2AAAAAAA_AAAAAAAA;
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assign vectorWContinuously = 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA;
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assign real1Continuously = 1.0;
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assign textHalfContinuously = "Hf";
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assign textLongContinuously = "Long64b";
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assign textContinuously = "Verilog Test module";
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assign binStringContinuously = 8'b10101010;
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assign octStringContinuously = 15'o25252; // 0b1010...
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assign hexStringContinuously = 64'hAAAAAAAAAAAAAAAA; // 0b1010...
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assign decStringCContinuously = 8'hAA;
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assign decStringSContinuously = 16'hAAAA;
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assign decStringIContinuously = 32'hAAAAAAAA;
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assign decStringQContinuously = 64'd12297829382473034410; // 0b1010...
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task automatic svForceValues();
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force onebit = 0;
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force intval = 32'h55555555;
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force vectorC = 8'h55;
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force vectorQ = 62'h15555555_55555555;
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force vectorW = 128'h55555555_55555555_55555555_55555555;
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force real1 = 123456.789;
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force textHalf = "T2";
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force textLong = "44Four44";
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force text = "lorem ipsum";
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force binString = 8'b01010101;
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force octString = 15'o52525;
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force hexString = 64'h5555555555555555;
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force decStringC = 8'h55;
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force decStringS = 16'h5555;
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force decStringI = 32'h55555555;
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force decStringQ = 64'd6148914691236517205;
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force onebitContinuously = 0;
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force intvalContinuously = 32'h55555555;
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force vectorCContinuously = 8'h55;
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force vectorQContinuously = 62'h15555555_55555555;
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force vectorWContinuously = 128'h55555555_55555555_55555555_55555555;
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force real1Continuously = 123456.789;
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force textHalfContinuously = "T2";
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force textLongContinuously = "44Four44";
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force textContinuously = "lorem ipsum";
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force binStringContinuously = 8'b01010101;
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force octStringContinuously = 15'o52525;
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force hexStringContinuously = 64'h5555555555555555;
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force decStringCContinuously = 8'h55;
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force decStringSContinuously = 16'h5555;
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force decStringIContinuously = 32'h55555555;
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force decStringQContinuously = 64'd6148914691236517205;
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endtask
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task automatic svPartiallyForceValues();
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force intval[15:0] = 16'h5555;
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force vectorC[3:0] = 4'h5;
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force vectorQ[30:0] = 31'h55555555;
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force vectorW[63:0] = 64'h55555555_55555555;
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force textHalf[7:0] = "2";
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force textLong[31:0] = "ur44";
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force text[63:0] = "em ipsum";
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force binString[3:0] = 4'b0101;
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force octString[6:0] = 7'o125;
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force hexString[31:0] = 32'h55555555;
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force decStringC[3:0] = 4'h5;
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force decStringS[7:0] = 8'h55;
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force decStringI[15:0] = 16'h5555;
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force decStringQ[31:0] = 32'd1431655765;
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force intvalContinuously[15:0] = 16'h5555;
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force vectorCContinuously[3:0] = 4'h5;
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force vectorQContinuously[30:0] = 31'h55555555;
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force vectorWContinuously[63:0] = 64'h55555555_55555555;
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force textHalfContinuously[7:0] = "2";
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force textLongContinuously[31:0] = "ur44";
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force textContinuously[63:0] = "em ipsum";
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force binStringContinuously[3:0] = 4'b0101;
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force octStringContinuously[6:0] = 7'o125;
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force hexStringContinuously[31:0] = 32'h55555555;
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force decStringCContinuously[3:0] = 4'h5;
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force decStringSContinuously[7:0] = 8'h55;
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force decStringIContinuously[15:0] = 16'h5555;
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force decStringQContinuously[31:0] = 32'd1431655765;
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endtask
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task automatic vpiPutString();
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integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting
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// called also causes simulation termination
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("putString()");
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`else
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vpiStatus = putString();
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`endif
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`else
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$stop; // This task only makes sense with Verilator, since other simulators ignore the "verilator forceable" metacomment.
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display(
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"C Test failed (vpi_put_value failed for string)");
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$stop;
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end
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endtask
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task automatic vpiTryInvalidPutOperations();
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integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting
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// called also causes simulation termination
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("tryInvalidPutOperations()");
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`else
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vpiStatus = tryInvalidPutOperations();
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`endif
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`else
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$stop; // This task only makes sense with Verilator, since it tests verilated_vpi.cpp
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display(
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"C Test failed (invalid vpi_put_value operation either succeeded, even though it should have failed, or produced an unexpected error message.)");
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$stop;
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end
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endtask
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task automatic vpiPutInertialDelay();
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integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting
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// called also causes simulation termination
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("putInertialDelay()");
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`else
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vpiStatus = putInertialDelay();
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`endif
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`else
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$stop; // This task only makes sense with Verilator, since it tests verilated_vpi.cpp
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display(
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"C Test failed (vpi_put_value with vpiInertialDelay failed)");
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$stop;
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end
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endtask
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task automatic vpiForceValues();
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integer vpiStatus = 1;
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("forceValues()");
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`else
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vpiStatus = forceValues();
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`endif
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`elsif IVERILOG
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vpiStatus = $forceValues;
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`elsif USE_VPI_NOT_DPI
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vpiStatus = $forceValues;
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`else
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vpiStatus = forceValues();
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display("C Test failed (could not force value)");
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$stop;
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end
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endtask
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task automatic svReleaseValues();
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release onebit;
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release intval;
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release vectorC;
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release vectorQ;
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release vectorW;
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release real1;
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release textHalf;
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release textLong;
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release text;
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release binString;
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release octString;
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release hexString;
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release decStringC;
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release decStringS;
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release decStringI;
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release decStringQ;
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release onebitContinuously;
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release intvalContinuously;
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release vectorCContinuously;
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release vectorQContinuously;
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release vectorWContinuously;
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release real1Continuously;
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release textHalfContinuously;
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release textLongContinuously;
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release textContinuously;
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release binStringContinuously;
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release octStringContinuously;
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release hexStringContinuously;
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release decStringCContinuously;
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release decStringSContinuously;
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release decStringIContinuously;
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release decStringQContinuously;
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endtask
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task automatic vpiReleaseValues();
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integer vpiStatus = 1;
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("releaseValues()");
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`else
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vpiStatus = releaseValues();
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`endif
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`elsif IVERILOG
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vpiStatus = $releaseValues;
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`elsif USE_VPI_NOT_DPI
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vpiStatus = $releaseValues;
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`else
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vpiStatus = releaseValues();
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display("C Test failed (could not release value)");
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$stop;
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end
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endtask
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task automatic vpiReleasePartiallyForcedValues();
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integer vpiStatus = 1;
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("releasePartiallyForcedValues()");
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`else
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vpiStatus = releasePartiallyForcedValues();
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`endif
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`elsif IVERILOG
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vpiStatus = $releasePartiallyForcedValues;
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`elsif USE_VPI_NOT_DPI
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vpiStatus = $releasePartiallyForcedValues;
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`else
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vpiStatus = releasePartiallyForcedValues();
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display("C Test failed (could not release value)");
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$stop;
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end
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endtask
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task automatic svCheckValuesForced();
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if(onebit != 0) $stop;
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if(intval != 32'h55555555) $stop;
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if(vectorC != 8'h55) $stop;
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if(vectorQ != 62'h15555555_55555555) $stop;
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if(vectorW != 128'h55555555_55555555_55555555_55555555) $stop;
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if(real1 != 123456.789) $stop;
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if(textHalf != "T2") $stop;
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if(textLong != "44Four44") $stop;
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if(text != "lorem ipsum") $stop;
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if(binString != 8'b01010101) $stop;
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if(octString != 15'o52525) $stop;
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if(hexString != 64'h5555555555555555) $stop;
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if(decStringC != 8'h55) $stop;
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if(decStringS != 16'h5555) $stop;
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if(decStringI != 32'h55555555) $stop;
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if(decStringQ != 64'd6148914691236517205) $stop;
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if(onebitContinuously != 0) $stop;
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if(intvalContinuously != 32'h55555555) $stop;
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if(vectorCContinuously != 8'h55) $stop;
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if(vectorQContinuously != 62'h15555555_55555555) $stop;
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if(vectorWContinuously != 128'h55555555_55555555_55555555_55555555) $stop;
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if(real1Continuously != 123456.789) $stop;
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if(textHalfContinuously != "T2") $stop;
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if(textLongContinuously != "44Four44") $stop;
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if(textContinuously != "lorem ipsum") $stop;
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if(binStringContinuously != 8'b01010101) $stop;
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if(octStringContinuously != 15'o52525) $stop;
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if(hexStringContinuously != 64'h5555555555555555) $stop;
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if(decStringCContinuously != 8'h55) $stop;
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if(decStringSContinuously != 16'h5555) $stop;
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if(decStringIContinuously != 32'h55555555) $stop;
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if(decStringQContinuously != 64'd6148914691236517205) $stop;
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endtask
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task automatic vpiCheckValuesForced();
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integer vpiStatus = 1;
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`ifdef VERILATOR
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`ifdef USE_VPI_NOT_DPI
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vpiStatus = $c32("checkValuesForced()");
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`else
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vpiStatus = checkValuesForced();
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`endif
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`elsif IVERILOG
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vpiStatus = $checkValuesForced;
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`elsif USE_VPI_NOT_DPI
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vpiStatus = $checkValuesForced;
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`else
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vpiStatus = checkValuesForced();
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`endif
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if (vpiStatus != 0) begin
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$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
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$display("C Test failed (value after forcing does not match expectation)");
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$stop;
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end
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endtask
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task automatic svCheckValuesPartiallyForced();
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if (intval != 32'hAAAA_5555) $stop;
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if (vectorC != 8'h A5) $stop;
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if (vectorQ != 62'h2AAAAAAAD5555555) $stop;
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if (vectorW != 128'hAAAAAAAA_AAAAAAAA_55555555_55555555) $stop;
|
|
if (textHalf != "H2") $stop;
|
|
if (textLong != "Lonur44") $stop;
|
|
if (text != "Verilog Tesem ipsum") $stop;
|
|
if (binString != 8'b1010_0101) $stop;
|
|
if (octString != 15'b01010101_1010101) $stop;
|
|
if (hexString != 64'hAAAAAAAA_55555555) $stop;
|
|
if (decStringC != 8'hA5) $stop;
|
|
if (decStringS != 16'hAA55) $stop;
|
|
if (decStringI != 32'hAAAA_5555) $stop;
|
|
if (decStringQ != 64'hAAAAAAAA_55555555) $stop;
|
|
|
|
if (intvalContinuously != 32'hAAAA_5555) $stop;
|
|
if (vectorCContinuously != 8'h A5) $stop;
|
|
if (vectorQContinuously != 62'h2AAAAAAAD5555555) $stop;
|
|
if (vectorWContinuously != 128'hAAAAAAAA_AAAAAAAA_55555555_55555555) $stop;
|
|
if (textHalfContinuously != "H2") $stop;
|
|
if (textLongContinuously != "Lonur44") $stop;
|
|
if (textContinuously != "Verilog Tesem ipsum") $stop;
|
|
if (binStringContinuously != 8'b1010_0101) $stop;
|
|
if (octStringContinuously != 15'b01010101_1010101) $stop;
|
|
if (hexStringContinuously != 64'hAAAAAAAA_55555555) $stop;
|
|
if (decStringCContinuously != 8'hA5) $stop;
|
|
if (decStringSContinuously != 16'hAA55) $stop;
|
|
if (decStringIContinuously != 32'hAAAA_5555) $stop;
|
|
if (decStringQContinuously != 64'hAAAAAAAA_55555555) $stop;
|
|
endtask
|
|
|
|
task automatic vpiCheckValuesPartiallyForced();
|
|
integer vpiStatus = 1;
|
|
`ifdef VERILATOR
|
|
`ifdef USE_VPI_NOT_DPI
|
|
vpiStatus = $c32("checkValuesPartiallyForced()");
|
|
`else
|
|
vpiStatus = checkValuesPartiallyForced();
|
|
`endif
|
|
`elsif IVERILOG
|
|
vpiStatus = $checkValuesPartiallyForced;
|
|
`elsif USE_VPI_NOT_DPI
|
|
vpiStatus = $checkValuesPartiallyForced;
|
|
`else
|
|
vpiStatus = checkValuesPartiallyForced();
|
|
`endif
|
|
|
|
if (vpiStatus != 0) begin
|
|
$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
|
|
$display("C Test failed (value after partial forcing does not match expectation)");
|
|
$stop;
|
|
end
|
|
endtask
|
|
|
|
task automatic svCheckValuesReleased();
|
|
if (onebit != 1) $stop;
|
|
if (intval != 32'hAAAAAAAA) $stop;
|
|
if (vectorC != 8'hAA) $stop;
|
|
if (vectorQ != 62'h2AAAAAAA_AAAAAAAA) $stop;
|
|
if (vectorW != 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA) $stop;
|
|
if (real1 != 1.0) $stop;
|
|
if (textHalf != "Hf") $stop;
|
|
if (textLong != "Long64b") $stop;
|
|
if (text != "Verilog Test module") $stop;
|
|
if (binString != 8'b10101010) $stop;
|
|
if (octString != 15'o25252) $stop;
|
|
if (hexString != 64'hAAAAAAAAAAAAAAAA) $stop;
|
|
if (decStringC != 8'hAA) $stop;
|
|
if (decStringS != 16'hAAAA) $stop;
|
|
if (decStringI != 32'hAAAAAAAA) $stop;
|
|
if (decStringQ != 64'd12297829382473034410) $stop;
|
|
|
|
if (onebitContinuously != 1) $stop;
|
|
if (intvalContinuously != 32'hAAAAAAAA) $stop;
|
|
if (vectorCContinuously != 8'hAA) $stop;
|
|
if (vectorQContinuously != 62'h2AAAAAAA_AAAAAAAA) $stop;
|
|
if (vectorWContinuously != 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA) $stop;
|
|
if (real1Continuously != 1.0) $stop;
|
|
if (textHalfContinuously != "Hf") $stop;
|
|
if (textLongContinuously != "Long64b") $stop;
|
|
if (textContinuously != "Verilog Test module") $stop;
|
|
if (binStringContinuously != 8'b10101010) $stop;
|
|
if (octStringContinuously != 15'o25252) $stop;
|
|
if (hexStringContinuously != 64'hAAAAAAAAAAAAAAAA) $stop;
|
|
if (decStringCContinuously != 8'hAA) $stop;
|
|
if (decStringSContinuously != 16'hAAAA) $stop;
|
|
if (decStringIContinuously != 32'hAAAAAAAA) $stop;
|
|
if (decStringQContinuously != 64'd12297829382473034410) $stop;
|
|
endtask
|
|
|
|
task automatic vpiCheckValuesReleased();
|
|
integer vpiStatus = 1;
|
|
`ifdef VERILATOR
|
|
`ifdef USE_VPI_NOT_DPI
|
|
vpiStatus = $c32("checkValuesReleased()");
|
|
`else
|
|
vpiStatus = checkValuesReleased();
|
|
`endif
|
|
`elsif IVERILOG
|
|
vpiStatus = $checkValuesReleased;
|
|
`elsif USE_VPI_NOT_DPI
|
|
vpiStatus = $checkValuesReleased;
|
|
`else
|
|
vpiStatus = checkValuesReleased();
|
|
`endif
|
|
|
|
if (vpiStatus != 0) begin
|
|
$write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus);
|
|
$display("C Test failed (value after releasing does not match expectation)");
|
|
$stop;
|
|
end
|
|
endtask
|
|
|
|
initial begin
|
|
`ifdef WAVES
|
|
$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
|
|
$dumpvars();
|
|
`endif
|
|
|
|
`ifdef VERILATOR
|
|
vpiPutString();
|
|
vpiTryInvalidPutOperations();
|
|
vpiPutInertialDelay();
|
|
`endif
|
|
|
|
// Wait a bit before triggering the force to see a change in the traces
|
|
#4 vpiForceValues();
|
|
|
|
// Time delay to ensure setting and checking values does not happen
|
|
// at the same time, so that the signals can have their values overwritten
|
|
// by other processes
|
|
#4 vpiCheckValuesForced();
|
|
svCheckValuesForced();
|
|
#4 vpiReleaseValues();
|
|
#4 vpiCheckValuesReleased();
|
|
svCheckValuesReleased();
|
|
|
|
// Force through VPI, release through Verilog
|
|
#4 vpiForceValues();
|
|
#4 vpiCheckValuesForced();
|
|
svCheckValuesForced();
|
|
#4 svReleaseValues();
|
|
#4 vpiCheckValuesReleased();
|
|
svCheckValuesReleased();
|
|
|
|
// Force through Verilog, release through VPI
|
|
#4 svForceValues();
|
|
#4 vpiCheckValuesForced();
|
|
svCheckValuesForced();
|
|
#4 vpiReleaseValues();
|
|
#4 vpiCheckValuesReleased();
|
|
svCheckValuesReleased();
|
|
|
|
// Force only some bits, check if __VforceRd yields correct signal,
|
|
// release through VPI
|
|
#4 svPartiallyForceValues();
|
|
#4 vpiCheckValuesPartiallyForced();
|
|
svCheckValuesPartiallyForced();
|
|
#4 vpiReleasePartiallyForcedValues();
|
|
#4 vpiCheckValuesReleased();
|
|
svCheckValuesReleased();
|
|
|
|
// Force only some bits, check if __VforceRd yields correct signal,
|
|
// release through Verilog
|
|
#4 svPartiallyForceValues();
|
|
#4 vpiCheckValuesPartiallyForced();
|
|
svCheckValuesPartiallyForced();
|
|
#4 svReleaseValues();
|
|
#4 vpiCheckValuesReleased();
|
|
svCheckValuesReleased();
|
|
|
|
|
|
#5 $display("*-* All Finished *-*");
|
|
$finish;
|
|
end
|
|
|
|
`ifdef TEST_VERBOSE
|
|
always @(posedge clk or negedge clk) begin
|
|
$display("time: %0t\tclk:%b", $time, clk);
|
|
|
|
$display("str1: %s", str1);
|
|
$display("delayed: %x", delayed);
|
|
|
|
$display("onebit: %x", onebit);
|
|
$display("intval: %x", intval);
|
|
$display("vectorC: %x", vectorC);
|
|
$display("vectorQ: %x", vectorQ);
|
|
$display("vectorW: %x", vectorW);
|
|
$display("real1: %f", real1);
|
|
$display("textHalf: %s", textHalf);
|
|
$display("textLong: %s", textLong);
|
|
$display("text: %s", text);
|
|
$display("binString: %x", binString);
|
|
$display("octString: %x", octString);
|
|
$display("hexString: %x", hexString);
|
|
$display("decStringC: %x", decStringC);
|
|
$display("decStringS: %x", decStringS);
|
|
$display("decStringI: %x", decStringI);
|
|
$display("decStringQ: %x", decStringQ);
|
|
|
|
$display("onebitContinuously: %x", onebitContinuously);
|
|
$display("intvalContinuously: %x", intvalContinuously);
|
|
$display("vectorCContinuously: %x", vectorCContinuously);
|
|
$display("vectorQContinuously: %x", vectorQContinuously);
|
|
$display("vectorWContinuously: %x", vectorWContinuously);
|
|
$display("real1Continuously: %f", real1Continuously);
|
|
$display("textHalfContinuously: %s", textHalfContinuously);
|
|
$display("textLongContinuously: %s", textLongContinuously);
|
|
$display("textContinuously: %s", textContinuously);
|
|
$display("binStringContinuously: %x", binStringContinuously);
|
|
$display("octStringContinuously: %x", octStringContinuously);
|
|
$display("hexStringContinuously: %x", hexStringContinuously);
|
|
$display("decStringCContinuously: %x", decStringCContinuously);
|
|
$display("decStringSContinuously: %x", decStringSContinuously);
|
|
$display("decStringIContinuously: %x", decStringIContinuously);
|
|
$display("decStringQContinuously: %x", decStringQContinuously);
|
|
|
|
$display("========================\n");
|
|
end
|
|
`endif
|
|
|
|
endmodule
|