22 lines
474 B
Systemverilog
22 lines
474 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(
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input logic [0:0][2:0] i,
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output logic o
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);
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always_comb begin
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o = 1'b0;
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// verilator unroll_full
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for (int n = 0 ; n < 3; ++n) begin
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o = o | i[n] == 3'd0; // Intentionally out of bounds
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end
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end
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endmodule
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