18 lines
594 B
Systemverilog
18 lines
594 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a, b, c, d;
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// Ranged cycle-delay in the inner arm is not lowerable: each length
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// in the range would admit a different offset set. IEEE 1800-2023
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// 16.9.10 is not well-defined under variable-length operands for our
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// fixed-length desugar, so reject with UNSUPPORTED.
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assert property (@(posedge clk)
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(a ##[1:3] b) within (c ##5 d));
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endmodule
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