92 lines
1.7 KiB
Systemverilog
92 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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wire q;
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logic d = 0, clear, preset;
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dff flipflop (
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q,
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d,
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clear,
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preset,
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clk
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);
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//clear and preset signals are in inverted logic
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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clear = 1;
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preset = 0;
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d = 0;
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end
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else if (cyc == 1) begin
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`checkh(q, 1);
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preset = 1;
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d = 1;
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end
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else if (cyc == 2) begin
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`checkh(q, 1);
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clear = 0;
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end
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else if (cyc == 3) begin
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`checkh(q, 0);
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preset = 0;
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end
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else if (cyc == 4) begin
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`checkh(q, 0);
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clear = 1;
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preset = 1;
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end
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else if (cyc == 5) begin
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`checkh(q, 1);
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d = 0;
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end
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else if (cyc == 6) begin
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`checkh(q, 0);
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d = 1;
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end
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else if (cyc == 7) begin
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`checkh(q, 1);
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end
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else if (cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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// From IEEE 1800-2023 10.6.1
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module dff (
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q,
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d,
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clear,
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preset,
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clock
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);
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output q;
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input d, clear, preset, clock;
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logic q;
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always @(clear or preset)
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if (!clear) assign q = 0;
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else if (!preset) assign q = 1;
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else deassign q;
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always @(posedge clock) q = d;
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endmodule
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