69 lines
2.2 KiB
Systemverilog
69 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// IEEE 1800-2023 16.14.6: if-gated procedural concurrent assertion vs
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// module-scope reference; counts must diverge to prove the gate is preserved.
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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reg rst_l;
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// Derive property operands from non-adjacent CRC bits.
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wire [1:0] req = {crc[6], crc[0]};
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wire gnt = crc[12];
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int count_gated = 0;
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int count_ref = 0;
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// Procedural concurrent assertion with inferred clock, guarded by
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// `if (cyc[0])`. The assertion attempt only starts on odd cycles.
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always @(negedge clk) begin
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if (cyc[0])
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assert property (disable iff (!rst_l) ((&req) |-> gnt))
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else count_gated <= count_gated + 1;
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end
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// Module-scope reference assertion with identical disable iff / property
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// but no procedural gating.
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assert property (@(negedge clk) disable iff (!rst_l) ((&req) |-> gnt))
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else count_ref <= count_ref + 1;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x rst_l=%b req=%b gnt=%b gated=%0d ref=%0d\n", $time, cyc, crc,
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rst_l, req, gnt, count_gated, count_ref);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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rst_l <= 1'b0;
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end
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else if (cyc == 3) begin
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rst_l <= 1'b1;
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end
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else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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// Questa 2022.3 golden: count_gated=5, count_ref=12.
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`checkd(count_gated, 5);
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`checkd(count_ref, 12);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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