35 lines
762 B
Systemverilog
35 lines
762 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk = 0;
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int cnt = 0;
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bit fire = 0;
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always #1 clk = ~clk;
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always_ff @(posedge clk) begin
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if (fire) cnt <= cnt + 1;
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end
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assert property (@(posedge clk) fire |-> (cnt == 0))
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$write("Assertion fired and passed: cnt=%0d\n", cnt);
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else begin
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$write("%%Error: sampled fire=1 cnt=%0d, expected preponed cnt 0\n", cnt);
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$stop;
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end
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initial begin
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@(posedge clk);
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fire <= 1;
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@(posedge clk);
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fire <= 0;
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repeat (2) @(posedge clk);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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