67 lines
2.3 KiB
Systemverilog
67 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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`ifdef verilator
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`define no_optimize(v) $c(v)
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`else
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`define no_optimize(v) (v)
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`endif
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module t ( /*AUTOARG*/);
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logic clk = 0;
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int imm_fails = 0, conc_fails = 0;
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logic a = 1'b1; // antecedent always true
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logic b = 1'b0; // consequent always false -> assertion always violates
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always #5 clk = ~clk;
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// Immediate assertion: assertion_type SIMPLE_IMMEDIATE (mask value 2).
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always @(posedge clk)
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ia :
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assert (b)
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else imm_fails = imm_fails + 1;
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// Concurrent assertion: assertion_type CONCURRENT (mask value 1).
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ca :
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assert property (@(posedge clk) a |-> b)
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else conc_fails = conc_fails + 1;
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int ctl;
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// posedge clk at t = 5, 15, 25, 35, 45, 55, 65, 75, 85, 95.
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initial begin
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// Phase A (t=0..): everything on. edge@5 -> imm+1, conc+1.
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#6; // t=6
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// Phase B: lock the on state, then $assertoff must be ignored while locked.
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$assertcontrol(1); // Lock, all types
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$assertoff; // ignored -> edges @15,@25 still fire both
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#24; // t=30
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// Phase C: unlock, then turn off only SIMPLE_IMMEDIATE via assertion_type filter.
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$assertcontrol(2); // Unlock
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$assertcontrol(4, 2); // Off, assertion_type = SIMPLE_IMMEDIATE only
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#20; // t=50: edges @35,@45 -> imm off, conc still on
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// Phase D: non-constant control_type and assertion_type re-enable the immediate.
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ctl = `no_optimize(3); // On
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$assertcontrol(ctl, `no_optimize(2)); // non-const On, SIMPLE_IMMEDIATE
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#20; // t=70: edges @55,@65 -> both on
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// Phase E: off everything, then a non-const action-control code (no runtime effect).
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$assertcontrol(4); // Off all
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ctl = `no_optimize(7); // Pass_Off (IEEE 1800-2023 Table 20-5 action control)
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$assertcontrol(ctl); // non-const action-control: evaluated at runtime, ignored
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#30; // t=100: edges @75,@85,@95 -> none
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$finish;
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end
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final begin
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// Concrete counts cross-checked against Questa 2022.3: imm_fails=5 conc_fails=7.
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if (imm_fails != 5 || conc_fails != 7) begin
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$display("%%Error: imm_fails=%0d (exp 5) conc_fails=%0d (exp 7)", imm_fails, conc_fails);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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end
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endmodule
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