verilator/test_regress/t/t_unoptflat_simple_2_bad.out

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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: 't.x'
wire [2:0] x;
^
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
t/t_unoptflat_simple_2.v:14: Example path: t.x
t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW
t/t_unoptflat_simple_2.v:14: Example path: t.x
%Warning-UNOPTFLAT: Widest candidate vars to split:
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12, can be split
%Warning-UNOPTFLAT: Most fanned out candidate vars to split:
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12, can be split
-Info: Adding /*verilator split_var*/ to variables above may resolve this warning.
%Error: Exiting due to