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Geza Lore
b4a0ca8ba6
Introduce a new DfgAstRd vertex, which holds an AstNodeExpr that is a reference to a variable. This enables tracking all read references in Dfg, which both enables more optimization, and allows inlining of expressions in place of the reference more intelligently (e.g, when the expression is only used once, and is not in a loop). This can get rid of 20-30% of temporary variables introduced in Dfg in some designs. Note V3Gate later got rid of a lot of those, this is a step towards making V3Gate redundant. The more intelligent expression inlining is worth ~10% runtime speed on some designs.
26 lines
533 B
Systemverilog
26 lines
533 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk = 1'b0;
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always #5 clk = ~clk;
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initial begin
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#300;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// Complicated way to write constant 0 that only Dfg can decipher
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wire [1:0] constant = 2'b0 ^ (({2{clk}} & ~{2{clk}}));
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always @(posedge constant[0]) begin
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$stop;
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end
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endmodule
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