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81 lines
2.8 KiB
Systemverilog
81 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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wire a = crc[0];
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wire b = crc[4];
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wire c = crc[8];
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wire cons_a = cyc < 1100;
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wire goto_a = cyc[1:0] != 0;
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int count_fail_257 = 0;
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int count_fail_cycles_513 = 0;
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int count_fail_threads_513 = 0;
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int count_fail_consrep_1025 = 0;
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int count_fail_consrep_range_1025 = 0;
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int count_fail_goto_1025 = 0;
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int count_fail_goto_range_1025 = 0;
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int count_cover_1025 = 0;
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// All N > prior kConsRepLimit=256 (pre-fix: V3AssertNfa crash at codegen).
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assert property (@(posedge clk) a [* 257] |-> b)
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else count_fail_257 <= count_fail_257 + 1;
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assert property (@(posedge clk) c |-> ##1 a [* 513])
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else count_fail_cycles_513 <= count_fail_cycles_513 + 1;
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// A blocking action counts all live threads rejected when the long run ends.
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assert property (@(posedge clk) cons_a [* 513])
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else if (cyc == 1100) count_fail_threads_513++;
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// One triggered attempt makes an off-by-one ring exit observable. Consecutive
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// repetition sees a long run; goto repetition advances across regular gaps.
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assert property (@(posedge clk) (cyc == 0) ##0 cons_a [* 1025: $] |-> cyc == 2047)
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else count_fail_consrep_1025++;
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assert property (@(posedge clk) (cyc == 0) ##0 cons_a [* 1: 1025] |-> cyc == 2047)
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else count_fail_consrep_range_1025++;
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cover sequence (@(posedge clk) a [* 1: 1025]) count_cover_1025++;
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assert property (@(posedge clk) (cyc == 0) ##0 goto_a [-> 1025] |-> cyc != 1366)
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else count_fail_goto_1025++;
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assert property (@(posedge clk) (cyc == 0) ##0 goto_a [-> 1: 1025] |-> cyc == 2047)
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else count_fail_goto_range_1025++;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc == 2047) begin
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`checkh(crc, 64'h91bd2213af2ba46e);
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`checkd(count_fail_257, 0);
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`checkd(count_fail_cycles_513, 666);
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`checkd(count_fail_threads_513, 513);
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`checkd(count_fail_consrep_1025, 76);
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`checkd(count_fail_consrep_range_1025, 1025);
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`checkd(count_fail_goto_1025, 1);
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`checkd(count_fail_goto_range_1025, 1025);
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`checkd(count_cover_1025, 2049);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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