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23 lines
516 B
Systemverilog
23 lines
516 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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logic a;
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logic b;
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} unpacked_struct_t;
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typedef union {
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logic a;
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logic b;
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} unpacked_union_t;
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module t;
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unpacked_struct_t [0:0][0:0] unpacked_struct_array;
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unpacked_union_t [0:0][0:0] unpacked_union_array;
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typedef struct {logic a;} [0:0][0:0] direct_unpacked_struct_array_t;
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endmodule
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