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68 lines
2.4 KiB
Systemverilog
68 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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// Test to check whether the following spec is properly implemented.
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// In IEEE 1800-2023 7.4.1 Packed arrays:
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// If a packed array is declared as signed, then the array viewed as a single
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// vector shall be signed. The individual elements of the array are unsigned
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// unless they are of a named type declared as signed.
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module t;
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typedef logic signed [2:0] named_t;
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typedef named_t [1:0] named_named_t;
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typedef logic signed [1:0][2:0] named_unnamed_t;
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named_named_t [1:0] named_named;
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named_t [1:0][1:0] named_2d;
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named_unnamed_t [1:0] named_unnamed;
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logic signed [1:0][1:0][2:0] unnamed;
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initial begin
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logic signed [11:0] whole_result;
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logic signed [5:0] slice_result;
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logic signed [2:0] element_result;
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// Set 1 to MSB(=sign bit)
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named_named = 12'b100000_000000;
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named_2d = 12'b100000_000000;
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named_unnamed = 12'b100000_000000;
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unnamed = 12'b100000_000000;
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whole_result = $signed((named_named >>> 1) >> 11);
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`checkd(whole_result, 0);
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slice_result = $signed((named_named[1] >>> 1) >> 5);
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`checkd(slice_result, 0);
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element_result = $signed((named_named[1][1] >>> 1) >> 2);
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`checkd(element_result, 1);
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whole_result = $signed((named_2d >>> 1) >> 11);
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`checkd(whole_result, 0);
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element_result = $signed((named_2d[1][1] >>> 1) >> 2);
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`checkd(element_result, 1);
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whole_result = $signed((named_unnamed >>> 1) >> 11);
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`checkd(whole_result, 0);
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slice_result = $signed((named_unnamed[1] >>> 1) >> 5);
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`checkd(slice_result, 1);
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element_result = $signed((named_unnamed[1][1] >>> 1) >> 2);
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`checkd(element_result, 0);
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whole_result = $signed((unnamed >>> 1) >> 11);
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`checkd(whole_result, 1);
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slice_result = $signed((unnamed[1] >>> 1) >> 5);
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`checkd(slice_result, 0);
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element_result = $signed((unnamed[1][1] >>> 1) >> 2);
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`checkd(element_result, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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