82 lines
3.3 KiB
Systemverilog
82 lines
3.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc, bump, result;
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logic foo;
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initial begin
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cyc = 0;
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foo = '1;
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end
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always @(posedge clk) begin
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if (($time != 0) && foo) bump <= bump + 1;
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if (($realtime != 0) && foo) bump <= bump + 1;
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if (($stime != 0) && foo) bump <= bump + 1;
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if (($bitstoreal(123) != 0) && foo) bump <= bump + 1;
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if (($itor(123) != 0) && foo) bump <= bump + 1;
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if (($signed(3) != 0) && foo) bump <= bump + 1;
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if (($realtobits(1.23) != 0) && foo) bump <= bump + 1;
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if (($rtoi(1.23) != 0) && foo) bump <= bump + 1;
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if (($unsigned(-3) != 0) && foo) bump <= bump + 1;
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if (($clog2(123) != 0) && foo) bump <= bump + 1;
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if (($ln(123) != 0) && foo) bump <= bump + 1;
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if (($log10(123) != 0) && foo) bump <= bump + 1;
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if (($exp(123) != 0) && foo) bump <= bump + 1;
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if (($sqrt(123) != 0) && foo) bump <= bump + 1;
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if (($pow(123, 2) != 0) && foo) bump <= bump + 1;
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if (($floor(1.23) != 0) && foo) bump <= bump + 1;
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if (($ceil(1.23) != 0) && foo) bump <= bump + 1;
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if (($sin(123) != 0) && foo) bump <= bump + 1;
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if (($cos(123) != 0) && foo) bump <= bump + 1;
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if (($tan(123) != 0) && foo) bump <= bump + 1;
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if (($asin(123) != 0) && foo) bump <= bump + 1;
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if (($acos(123) != 0) && foo) bump <= bump + 1;
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if (($atan(123) != 0) && foo) bump <= bump + 1;
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if (($atan2(123, 2) != 0) && foo) bump <= bump + 1;
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if (($hypot(123, 2) != 0) && foo) bump <= bump + 1;
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if (($sinh(123) != 0) && foo) bump <= bump + 1;
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if (($cosh(123) != 0) && foo) bump <= bump + 1;
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if (($tanh(123) != 0) && foo) bump <= bump + 1;
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if (($asinh(123) != 0) && foo) bump <= bump + 1;
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if (($acosh(123) != 0) && foo) bump <= bump + 1;
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if (($atanh(123) != 0) && foo) bump <= bump + 1;
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if (($countbits(123, 2) != 0) && foo) bump <= bump + 1;
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if (($onehot(123) != 0) && foo) bump <= bump + 1;
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if ($isunknown(foo) && foo) bump <= bump + 1;
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if (($countones(123) != 0) && foo) bump <= bump + 1;
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if (($onehot0(123) != 0) && foo) bump <= bump + 1;
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if (($sampled(foo) != 0) && foo) bump <= bump + 1;
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if (($fell(foo) != 0) && foo) bump <= bump + 1;
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if (($changed(foo) != 0) && foo) bump <= bump + 1;
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if (($rose(foo) != 0) && foo) bump <= bump + 1;
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if (($stable(foo) != 0) && foo) bump <= bump + 1;
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if (($past(foo) != 0) && foo) bump <= bump + 1;
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if (($random != 0) && foo) bump <= bump + 1;
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if (($dist_erlang(result, 2, 3) != 0) && foo) bump <= bump + 1;
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if (($dist_normal(result, 2, 3) != 0) && foo) bump <= bump + 1;
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if (($dist_t(result, 2) != 0) && foo) bump <= bump + 1;
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if (($dist_chi_square(result, 2) != 0) && foo) bump <= bump + 1;
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if (($dist_exponential(result, 2) != 0) && foo) bump <= bump + 1;
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if (($dist_poisson(result, 2) != 0) && foo) bump <= bump + 1;
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if (($dist_uniform(result, 2, 3) != 0) && foo) bump <= bump + 1;
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if (($sformatf("abc") != "abc") && foo) bump <= bump + 1;
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if (foo && foo) bump <= bump + 1;
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cyc <= cyc + 1;
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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