120 lines
6.4 KiB
Verilog
120 lines
6.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// parameters for array sizes
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localparam WA = 4; // address dimension size
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localparam WB = 4; // bit dimension size
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localparam NO = 10; // number of access events
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// 2D packed arrays
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logic [WA-1:0] [WB-1:0] array_bg; // big endian array
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/* verilator lint_off LITENDIAN */
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logic [0:WA-1] [0:WB-1] array_lt; // little endian array
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/* verilator lint_on LITENDIAN */
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integer cnt = 0;
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// big endian
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'bx)
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if (cnt[30:2]==0) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }};
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]==0) begin end
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else if (cnt[30:2]==1) array_bg = '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]==2) array_bg = '{0:4, 1:5, 2:6, 3:7};
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else if (cnt[30:2]==3) array_bg = '{default:13};
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else if (cnt[30:2]==4) array_bg = '{2:15, default:13};
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else if (cnt[30:2]==5) array_bg = '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]==6) array_bg = '{WA { {3'b101, {WB/2-1{2'b10}}} }};
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else if (cnt[30:2]==7) array_bg = '{WA { {WB/2-1{2'b10}} }};
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else if (cnt[30:2]==8) array_bg [WA/2-1:0 ] = '{WA/2{ {WB/2 {2'b10}} }};
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else if (cnt[30:2]==9) array_bg [WA -1:WA/2] = '{WA/2{ {WB/2 {2'b01}} }};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]==0) begin if (array_bg !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==1) begin if (array_bg !== 16'b0011001000010000) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==2) begin if (array_bg !== 16'b0111011001010100) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==3) begin if (array_bg !== 16'b1101110111011101) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==4) begin if (array_bg !== 16'b1101111111011101) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==5) begin if (array_bg !== 16'b1010101010101010) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==6) begin if (array_bg !== 16'b0110011001100110) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==7) begin if (array_bg !== 16'b0010001000100010) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==8) begin if (array_bg !== 16'b10101010xxxxxxxx) begin $display("%b", array_bg); $stop(); end end
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else if (cnt[30:2]==9) begin if (array_bg !== 16'bxxxxxxxx10101010) begin $display("%b", array_bg); $stop(); end end
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end
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// little endian
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always @ (posedge clk)
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if (cnt[1:0]==2'd0) begin
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// initialize to defaults (all bits 1'bx)
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if (cnt[30:2]==0) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }};
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else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }};
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end else if (cnt[1:0]==2'd1) begin
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// write data into whole or part of the array using literals
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if (cnt[30:2]==0) begin end
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else if (cnt[30:2]==1) array_lt = '{ 3 ,2 ,1, 0 };
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else if (cnt[30:2]==2) array_lt = '{3:4, 2:5, 1:6, 0:7};
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else if (cnt[30:2]==3) array_lt = '{default:13};
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else if (cnt[30:2]==4) array_lt = '{1:15, default:13};
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else if (cnt[30:2]==5) array_lt = '{WA { {WB/2 {2'b10}} }};
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else if (cnt[30:2]==6) array_lt = '{WA { {3'b101, {WB/2-1{2'b10}}} }};
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else if (cnt[30:2]==7) array_lt = '{WA { {WB/2-1{2'b10}} }};
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else if (cnt[30:2]==8) array_lt [0 :WA/2-1] = '{WA/2{ {WB/2 {2'b10}} }};
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else if (cnt[30:2]==9) array_lt [WA/2:WA -1] = '{WA/2{ {WB/2 {2'b01}} }};
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end else if (cnt[1:0]==2'd2) begin
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// chack array agains expected value
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if (cnt[30:2]==0) begin if (array_lt !== 16'bxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==1) begin if (array_lt !== 16'b0011001000010000) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==2) begin if (array_lt !== 16'b0111011001010100) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==3) begin if (array_lt !== 16'b1101110111011101) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==4) begin if (array_lt !== 16'b1101111111011101) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==5) begin if (array_lt !== 16'b1010101010101010) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==6) begin if (array_lt !== 16'b0110011001100110) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==7) begin if (array_lt !== 16'b0010001000100010) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==8) begin if (array_lt !== 16'b10101010xxxxxxxx) begin $display("%b", array_lt); $stop(); end end
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else if (cnt[30:2]==9) begin if (array_lt !== 16'bxxxxxxxx10101010) begin $display("%b", array_lt); $stop(); end end
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end
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endmodule
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