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Geza Lore
ce77bac99a
Added an algorithm that can break some combinational cycles in DFG, by attempting to trace driver logic until we escape the cycle. This can eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code: ```systemverilog assign a[0] = .....; assign a[1] = ~a[0]; ```
61 lines
1.3 KiB
C++
61 lines
1.3 KiB
C++
//
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// DESCRIPTION: Verilator: DFG optimizer equivalence testing
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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//
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#include <verilated.h>
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#include <verilated_cov.h>
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#include <Vopt.h>
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#include <Vref.h>
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#include <iostream>
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void rngUpdate(uint64_t& x) {
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x ^= x << 13;
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x ^= x >> 7;
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x ^= x << 17;
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}
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int main(int, char**) {
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// Create contexts
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VerilatedContext ctx;
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// Create models
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Vref ref{&ctx};
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Vopt opt{&ctx};
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uint64_t rand_a = 0x5aef0c8dd70a4497;
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uint64_t rand_b = 0xf0c0a8dd75ae4497;
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uint64_t srand_a = 0x00fa8dcc7ae4957;
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uint64_t srand_b = 0x0fa8dc7ae3c9574;
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for (size_t n = 0; n < 200000; ++n) {
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// Update rngs
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rngUpdate(rand_a);
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rngUpdate(rand_b);
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rngUpdate(srand_a);
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rngUpdate(srand_b);
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// Assign inputs
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ref.rand_a = opt.rand_a = rand_a;
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ref.rand_b = opt.rand_b = rand_b;
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ref.srand_a = opt.srand_a = srand_a;
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ref.srand_b = opt.srand_b = srand_b;
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// Evaluate both models
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ref.eval();
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opt.eval();
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// Check equivalence
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#include "checks.h"
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// increment time
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ctx.timeInc(1);
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}
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std::cout << "*-* All Finished *-*\n";
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}
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