15 lines
383 B
Systemverilog
15 lines
383 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a, b, c, d;
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// Range delay in intersect operand is unsupported
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assert property (@(posedge clk)
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(a ##[1:5] b) intersect (c ##2 d));
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endmodule
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