115 lines
2.0 KiB
Systemverilog
115 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkt(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0t exp=%0t (%t !== %t)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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initial begin
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static int x = 0;
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fork : fork_blk
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begin
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#1;
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disable fork_blk; // Disables both forked processes
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$stop;
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end
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begin
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`checkt($time, 0);
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x = 1;
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#2;
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$stop;
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end
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join_none
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#1;
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if (x != 1) begin
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$display(x);
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$stop;
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end
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end
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initial begin
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static int y = 0;
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fork
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begin : fork_branch
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#1;
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disable fork_branch; // Disables only this branch of the fork
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$stop;
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end
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begin
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`checkt($time, 0);
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y = 1;
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#2;
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`checkt($time, 2);
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y = 2;
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end
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join_none
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#1;
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if (y != 1) begin
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$display(y);
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$stop;
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end
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#1;
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if (y != 2) begin
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$display(y);
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$stop;
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end
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end
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initial begin
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fork : fork_blk2
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begin
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`checkt($time, 0);
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disable fork_blk2;
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$stop;
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end
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begin
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`checkt($time, 0);
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#1 $stop;
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end
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join_none
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end
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initial begin
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fork : fork_blk3
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begin
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`checkt($time, 0);
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#1 $stop;
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end
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begin
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`checkt($time, 0);
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disable fork_blk3;
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$stop;
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end
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join_none
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end
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initial begin
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fork : fork_blk4
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begin
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`checkt($time, 0);
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if ($c("false")) begin
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disable fork_blk4;
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$stop;
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end
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#1;
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end
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begin
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`checkt($time, 0);
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#1;
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`checkt($time, 1);
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end
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join_none
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end
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initial begin
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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