verilator/test_regress
Krzysztof Bieganski 97add4d57a
Fix null access on optimized-out fork statements (#3658)
`V3SchedTiming` currently assumes that if a fork still exists, it must
have statements within it (otherwise it would have been deleted by
`V3Timing`). However, in a case like this:
```
module t;
    reg a;
    initial fork a = 1; join
endmodule
```
the assignment in the fork is optimized out by `V3Dead` after
`V3Timing`. This leads to `V3SchedTiming` accessing fork's `stmtsp`
pointer, which at this point is null. This patch addresses that issue.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-10-06 15:38:59 +02:00
..
t Fix null access on optimized-out fork statements (#3658) 2022-10-06 15:38:59 +02:00
.gdbinit Delay parsing of associative arrays until dtypes known. 2020-06-09 07:13:40 -04:00
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Copyright year update. 2022-01-01 08:26:40 -05:00
Makefile Copyright year update. 2022-01-01 08:26:40 -05:00
Makefile_obj Implement 'forceable' attribute 2022-01-16 15:31:37 +00:00
driver.pl Merge branch 'master' into develop-v5 2022-09-22 17:33:36 +01:00
input.vc Internal coverage improvements 2020-09-18 21:27:36 -04:00
input.xsim.vc Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00