37 lines
859 B
Systemverilog
37 lines
859 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Matthew Ballance
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// SPDX-License-Identifier: CC0-1.0
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// Test basic functional coverage sampling
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module t (/*AUTOARG*/);
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/* verilator lint_off UNSIGNED */
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logic [3:0] data;
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int cyc = 0;
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covergroup cg;
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coverpoint data {
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bins low = {[0:3]};
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bins mid = {[4:7]};
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bins high = {[8:15]};
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}
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endgroup
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cg cg_inst;
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initial begin
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cg_inst = new;
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// Sample different values
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data = 1; cg_inst.sample();
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data = 5; cg_inst.sample();
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data = 10; cg_inst.sample();
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data = 2; cg_inst.sample(); // low hit twice
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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