59 lines
1.4 KiB
Systemverilog
59 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test module designed to generate multiple small CFuncs that can be inlined
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// Uses generate to create multiple sub-module instances
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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parameter CNT = 8;
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wire [31:0] w [CNT:0];
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reg [31:0] w0;
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assign w[0] = w0;
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// Generate multiple sub-modules - each creates CFuncs that can be inlined
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generate
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for (genvar g=0; g<CNT; g++) begin : gen_sub
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sub sub_inst (.clk(clk), .i(w[g]), .z(w[g+1]));
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end
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endgenerate
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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w0 <= 32'h10;
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end
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else if (cyc==10) begin
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// Each sub adds 1, so final value is 0x10 + 8 = 0x18
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if (w[CNT] !== 32'h18) begin
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$write("%%Error: w[CNT]=%0x, expected 0x18\n", w[CNT]);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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// Small sub-module that generates inlineable CFuncs
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module sub (input clk, input [31:0] i, output reg [31:0] z);
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reg [7:0] local_a;
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reg [7:0] local_b;
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always @(posedge clk) begin
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local_a <= i[7:0];
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local_b <= 8'd1;
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z <= i + {24'b0, local_b};
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end
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endmodule
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