87 lines
1.7 KiB
Systemverilog
Executable File
87 lines
1.7 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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class RandomValue;
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rand int value;
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constraint small_int_c {
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value < 10;
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}
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task disable_val();
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value.rand_mode(0);
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endtask
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endclass
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class Base;
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rand RandomValue v = new;
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endclass
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class Foo extends Base;
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endclass
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package uvm_pkg;
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virtual class uvm_object;
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endclass
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class uvm_sequence_item;
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endclass
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virtual class uvm_sequencer_param_base;
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function void send_request(uvm_sequence_item t);
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uvm_sequence_item par;
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if (0 == par.randomize()) begin
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end
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endfunction
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endclass
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class uvm_reg_item extends uvm_sequence_item;
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rand uvm_object extension;
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endclass
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class uvm_reg_field extends uvm_object;
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rand int value;
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virtual function bit get_rand_mode();
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return bit'(value.rand_mode());
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endfunction
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endclass
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endpackage
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module t_constraint_global_randMode;
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import uvm_pkg::*;
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class reg_r extends uvm_object;
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rand int value;
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local rand uvm_reg_field _dummy;
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constraint _dummy_is_reg {_dummy.value == value;}
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function new();
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_dummy = new;
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endfunction
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endclass
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initial begin
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Foo d;
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Base b;
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reg_r r;
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// Test 1: Member class with randmode
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d = new;
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b = d;
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b.v.disable_val();
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b.v.value = 11;
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/* verilator lint_off WIDTHTRUNC */
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if (bit'(b.randomize())) $stop;
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if (b.v.value != 11) $stop;
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// Test 2: Member class without randmode
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r = new;
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if (!r.randomize()) $stop;
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/* verilator lint_on WIDTHTRUNC */
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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