70 lines
1.4 KiB
Systemverilog
70 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Disabling a module task by its local name in one module instance must not
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// terminate the same task declaration's activation in another module instance.
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// Each module instance and task definition creates a distinct hierarchical scope.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module child (
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input bit do_disable,
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output bit survived,
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output bit done
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);
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task automatic run();
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#5;
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survived = 1'b1;
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endtask
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initial begin
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fork
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run();
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join_none
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if (do_disable) begin
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#1;
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disable run;
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end
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else begin
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#6;
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end
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done = 1'b1;
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end
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endmodule
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module t;
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bit survived0;
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bit done0;
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bit survived1;
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bit done1;
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child child0 (
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.do_disable(1'b1),
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.survived(survived0),
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.done(done0)
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);
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child child1 (
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.do_disable(1'b0),
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.survived(survived1),
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.done(done1)
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);
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initial begin
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#8;
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`checkd(done0, 1'b1);
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`checkd(done1, 1'b1);
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`checkd(survived0, 1'b0);
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`checkd(survived1, 1'b1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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