verilator/test_regress
Geza Lore 3f89bdcfac
Defer conversion of set flag based AssignDlys (#5091)
No functional change. Postpone the conversion of all AstAssignDlys that
use the 'VdlySet' scheme for array LHSs until after the complete
traversal of the netlist. The next patch takes advantage of this by
using some extra information also gathered through the traversal to
change the conversion.

AstAssignDlys inside suspendable or fork are not deferred and are
processed identical to the previous version.

There are some TODOs in this patch that are fixed in the next patch.

Output code perturbed due to variable ordering.

MULTIDRIVEN message ordering perturbed due to processing order change.
2024-05-02 00:24:00 +01:00
..
t Defer conversion of set flag based AssignDlys (#5091) 2024-05-02 00:24:00 +01:00
.gdbinit Revert .gdbinit modified by accident. (#4330) 2023-06-30 16:57:31 -04:00
.gitignore
CMakeLists.txt Copyright year update 2024-01-01 03:19:59 -05:00
Makefile Make installation relocatable, and the installation testable (#4927) 2024-03-01 00:08:28 +00:00
Makefile_obj Copyright year update 2024-01-01 03:19:59 -05:00
driver.pl tests: disable ASLR for t_trace_ub_misaligned_address (#5075) 2024-04-29 15:38:00 +01:00
input.vc Tests: Avoid verilated.v include in most tests 2024-02-27 18:08:37 -05:00
input.xsim.vc Tests: Avoid verilated.v include in most tests 2024-02-27 18:08:37 -05:00