47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface my_if;
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logic sig_a, sig_b, sig_c, sig_d;
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modport mp1(input .a(sig_a), output .b(sig_b));
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modport mp2(input .a(sig_c), output .b(sig_d));
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endinterface
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module mod1 (
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my_if.mp1 i
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);
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assign i.b = i.a;
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endmodule
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module mod2 (
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my_if.mp2 i
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);
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assign i.b = i.a;
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endmodule
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module top ();
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my_if myIf ();
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assign myIf.sig_a = 1'b1, myIf.sig_c = 1'b1;
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mod1 mod1Instance (myIf);
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mod2 mod2Instance (myIf);
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initial begin
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#1;
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`checkh(myIf.sig_a, myIf.sig_b);
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`checkh(myIf.sig_c, myIf.sig_d);
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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