Files
verilator/include
Geza Lore 0e769d42a1 Optimize trigger evaluation
Pack the elements of VlTriggerVec as dense bits (instead of a 1 byte
bool per bit), and check whether they are set on a word granularity.
This effectively transforms conditions of the form `if (trig.at(0) |
trig.at(2) | trig.at(64))` into `if (trig.word(0) & 0x5 | trig.word(1) &
0x1)`. This improves OpenTitan ST by about 1%, worth more on some other
designs.
2023-04-24 09:09:36 +02:00
..
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-04-24 09:09:36 +02:00
2023-01-01 10:18:39 -05:00
2023-01-01 10:18:39 -05:00
2023-04-24 09:09:36 +02:00
2023-01-01 10:18:39 -05:00