61 lines
1.5 KiB
Systemverilog
61 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk,
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d
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);
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input clk;
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input d;
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wire delayed_CLK;
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wire delayed_D;
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reg notifier;
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wire [1:0] BL_X = 2'b11;
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wire [5:0] BL_X2;
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wire BL_0;
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wire [3:0] BL_1 = 4'b1100;
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logic[3:0] sh1 = 1;
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logic[3:0] sh2 = 2;
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logic[3:0] sh3 = 3;
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logic[3:0] sh4 = 4;
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int cyc = 0;
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specify
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$setuphold (posedge clk, negedge d, 0, 0, notifier,,, delayed_CLK, delayed_D);
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$setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4);
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$setuphold (posedge clk, negedge d, 0, 0);
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$setuphold (posedge clk, negedge d, (0:0:0), (0:0:0));
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$setuphold (posedge clk, negedge d, 0, 0,,,,,);
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$setuphold (posedge clk &&& sh1, BL_X[0], 0, 0, ,,,delayed_CLK, BL_0);
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$setuphold (posedge clk &&& sh1, BL_1, 0, 0, ,,,delayed_CLK, BL_X2[4:1]);
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endspecify
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initial begin
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if (sh1 != sh2 || sh3 != sh4) begin
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$stop;
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end
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if (BL_0 != BL_X[0] || BL_1 != BL_X2[4:1]) begin
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$stop;
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end
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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$display("%d %d", clk, delayed_CLK);
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if (delayed_CLK != clk || delayed_D != d) begin
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$stop;
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end
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if (cyc == 10) begin
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$display("*-* All Finished *-*");
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$finish;
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end
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end
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endmodule
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