19 lines
416 B
Systemverilog
19 lines
416 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event e;
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logic v = 0;
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initial #1 begin
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fork
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#0 if (v) $finish;
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else $stop;
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join_none
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->e;
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end
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initial @e v = 1;
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endmodule
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