verilator/test_regress/t/t_net_delay.out

8 lines
466 B
Plaintext

%Warning-ASSIGNDLY: t/t_net_delay.v:17:11: Ignoring timing control on this assignment/primitive due to --no-timing
: ... In instance t
17 | assign #4 val2 = cyc;
| ^
... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Error: Exiting due to