35 lines
649 B
Systemverilog
35 lines
649 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface apb_if (
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input bit clk
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);
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wire [31:0] paddr;
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wire [31:0] prdata;
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clocking mck @(posedge clk);
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output paddr;
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input prdata;
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// Some UVM tests declare this sequence but never use it
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// so we defer UNSUPPORTED until usage point
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sequence at_posedge;
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1;
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endsequence : at_posedge
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endclocking
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endinterface
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module t (
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input clk
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);
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apb_if ifc(clk);
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initial $finish;
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endmodule
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